=> setenv fit_addr_r 0x0a000000 => load mmc 0:4 ${fit_addr_r} fitImage.itb 25332224 bytes read in 182 ms (132.7 MiB/s) => spl export fdt ${fit_addr_r} ## Loading kernel (any) from FIT Image at 0a000000 ... Using 'standard' configuration Trying 'kernel' kernel subimage Description: Kernel Type: Kernel Image Compression: uncompressed Data Start: 0x0a0000b4 Data Size: 13391880 Bytes = 12.8 MiB Architecture: AArch64 OS: Linux Load Address: 0x02000000 Entry Point: 0x02000000 Hash algo: sha1 Hash value: ee1221a89308e82a18812d48a319745f594eceff Verifying Hash Integrity ... sha1+ OK ## Loading ramdisk (any) from FIT Image at 0a000000 ... Using 'standard' configuration Trying 'initrd' ramdisk subimage Description: Initrd Type: RAMDisk Image Compression: uncompressed Data Start: 0x0aceb77c Data Size: 11783404 Bytes = 11.2 MiB Architecture: AArch64 OS: Linux Load Address: unavailable Entry Point: unavailable Hash algo: sha1 Hash value: d14ed09d0b2c6787faa4535a7e0e1453e5484c19 Verifying Hash Integrity ... sha1+ OK ## Loading fdt (any) from FIT Image at 0a000000 ... Using 'standard' configuration Trying 'fdt' fdt subimage Description: DTB Type: Flat Device Tree Compression: uncompressed Data Start: 0x0acc5998 Data Size: 154898 Bytes = 151.3 KiB Architecture: AArch64 Load Address: 0x12000000 Hash algo: sha1 Hash value: 5d7862f65d5c9ad5bf126c83b521b8e350c2ca02 Verifying Hash Integrity ... sha1+ OK Loading fdt from 0x0acc5998 to 0x12000000 Booting using the fdt blob at 0x12000000 Working FDT set to 12000000 Loading Kernel Image to 2000000 Loading Ramdisk to ec3c6000, end ecf02cec ... OK Loading Device Tree to 00000000ec39d000, end 00000000ec3c5d11 ... OK Working FDT set to ec39d000 subcommand failed (err=-1) subcommand failed (err=-1) Loading Device Tree to 00000000ec371000, end 00000000ec39cd11 ... OK Working FDT set to ec371000 Argument image is now in RAM: 0x00000000ec371000 WARN: FDT size > CMD_SPL_WRITE_SIZE => mmc write ${fit_addr_r} 0x1000 49477 MMC write: dev # 0, block # 4096, count 300151 ... 300151 blocks written: OK => reset resetting ... DDR 9fa84341ce typ 24/09/06-09:51:11,fwver: v1.18 ch0 ttot10 ch1 ttot10 ch2 ttot10 ch3 ttot10 ch0 ttot18 LPDDR4X, 2112MHz channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB ch1 ttot18 channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB ch2 ttot18 channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB ch3 ttot18 channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB Manufacturer ID:0xff DQS rds:l0,h1 CH0 RX Vref:28.5%, TX Vref:23.8%,23.8% DQ rds:h1 h5 l0 l0 h1 h3 h1 h1, h4 h3 h1 h1 h2 l0 h4 h3 DQS rds:l0,h1 CH1 RX Vref:27.5%, TX Vref:22.8%,22.8% DQ rds:h6 l0 h2 l0 h3 h7 h1 h3, l0 h3 h4 h2 h1 l0 h1 h7 DQS rds:h1,h1 CH2 RX Vref:29.7%, TX Vref:21.8%,21.8% DQ rds:h2 h3 h5 h2 h7 h2 h1 h3, l0 h4 h5 l0 h6 h4 h7 h2 DQS rds:h1,h1 CH3 RX Vref:29.7%, TX Vref:21.8%,20.8% DQ rds:h6 h1 h3 l0 h3 h1 h5 h5, h6 h1 h1 h3 h4 h5 h3 h1 stride=0x2, ddr_config=0x4 hash ch_mask0-1 0x20 0x40, bank_mask0-3 0xa00 0x1400 0x2800 0x0, rank_mask0 0x401000 change to F1: 528MHz ch0 ttot10 ch1 ttot10 ch2 ttot10 ch3 ttot10 change to F2: 1068MHz ch0 ttot14 ch1 ttot14 ch2 ttot12 ch3 ttot14 change to F3: 1560MHz ch0 ttot16 ch1 ttot16 ch2 ttot14 ch3 ttot16 change to F0: 2112MHz ch0 ttot18 ch1 ttot18 ch2 ttot18 ch3 ttot18 out U-Boot SPL 2025.07-rc1 (Jan 01 1980 - 00:00:00 +0000) alloc space exhausted ptr 1828dc0 limit 200000 Could not get FIT buffer of 25332224 bytes check CONFIG_SPL_SYS_MALLOC_SIZE